The present invention relates generally to spintronic (spin electronic) device, comprising semiconductor structures in combination with ferromagnetic components. More specifically, it relates to information storage of integrated circuit memory devices using spintronic memory cells.
Semiconductor integrated circuit (IC) memory devices have replaced magnetic-core memory devices due to their lower fabrication cost and higher performance. An IC memory circuit includes a repeated array of memory cells which store one state of a two state information (0 or 1), or multi-state information (for example, 00, 01, 10, or 11 of 4 states), together with support circuitry such as a row decoder, a column decoder, a write circuit to write to the memory cell array, a control circuitry to select the correct memory cell, and a sense amplifier to amplify the signal.
One early memory circuit is a flip-flop that has an output that is stable for only one of two possible voltage levels. SRAM (static random access memory) circuit stores information in flip-flops where the information can be read from any memory cell at random (random access memory), and where the stored information can be kept indefinitely as long as the circuit receives power.
The next generation memory cell is a DRAM (dynamic random access memory) cell. A DRAM cell typically consists of a transistor and a capacitor. The capacitor stores information in the form of electrical charge and the transistor provides access to the capacitor. Because of the inherent leakage of the capacitor charge, DRAM cells must be rewritten or refreshed at frequent intervals.
SRAM and DRAM memories cannot retain the stored information without a power source, therefore they belong to a class of memory called volatile memory. Another class of memory is called non-volatile memory which will still retain the stored information even after the power is turned off.
A typical non-volatile memory is ferroelectric random access memory (FRAM). Similar to a DRAM cell, a FRAM cell consists of an access transistor and a storage capacitor. The difference is that FRAM cell uses ferroelectric material for its capacitor dielectric wherein the stored information is the polarization of the ferroelectric material. Ferroelectric material can be polarized by an electric field with a polarization lifetime of about 10 years.
Recent developments of materials that have changeable electrical resistance have introduced a new kind of non-volatile memory, called RRAM (resistive random access memory). The basic component of a RRAM cell is a variable resistor. The variable resistor can be programmed to have high resistance or low resistance (in two-state memory circuits), or any intermediate resistance value (in multi-state memory circuits). The different resistance values of the RRAM cell represent the information stored in the RRAM circuit.
The advantages of RRAM are the simplicity of the circuit which leads to smaller devices, the non-volatile characteristic of the resistor memory cell, and the stability of the memory state.
Since resistor is a passive component and cannot actively influence nearby electrical components, a basic RRAM cell can be just a variable resistor, arranged in a cross point resistor network to form a cross point memory array. To prevent cross talk or parasitic current path, a RRAM cell can further include a diode, and this combination is sometimes called a 1R1D (or 1D1R) cross point memory cell. To provide better access, a RRAM can include an access transistor, as in DRAM or FRAM cell, and this combination is sometimes called a 1R1T (or 1T1R) cross point memory cell.
The resistance states of the RRAM can be represented by different techniques such as structural, polarization, or magnetization state. Chalcogenide alloy is an example of structural state RRAM device. Chalcogenide alloys can exhibit two different stable reversible structural phases, namely an amorphous phase with high electrical resistance and a polycrystalline phase with lower electrical resistance. Resistive heating by an electrical current pulse can change the phases of the chalcogenide materials. One example of polarization state is a polymer memory element. The resistance state of a polymer memory element is dependent upon the orientation of polarization of the polymer molecules. The polarization of a polymer memory element can be written by applying an electric field.
MRAM (magnetic random access memory) is another class of RRAM circuits using magnetic properties for storing information based on magnetoresistance effect wherein the resistance of a magnetic material can be programmed. The magnetoresistance effect in MRAM devices are caused by the spins of electrons (corresponding to the rotation of the electron around its own axis).
In ferromagnetic materials, the electron spins can be aligned in one direction under the influence of an external field, and can keep their alignment even after the external field is removed (the hysteresis effect). At high temperatures (above Curie temperature), the ferromagnetic materials become paramagnetic (non-magnetic) because of the loss of the spin alignment due to high thermal energy.
In an MRAM cell employing magnetoresistance effect, conduction carriers (electrons or holes) with certain spins alignment are generated from a spin-polarized ferromagnetic source, and are injected into a non-ferromagnetic channel, and then detected at a spin-analyzer ferromagnetic drain. The conduction carriers are allowed to move more freely from the ferromagnetic source to the ferromagnetic drain if the magnetization in those source and drain are parallel than if they are antiparallel or partially antiparallel. The variation of the resistance is the magnetoresistance effect and the device is often called a spin valve device in view of the fact that the magnetization states of the ferromagnetic source and drain act like a valve for spin-polarized carriers.
In the typical spin valve devices, the non-ferromagnetic channel is a non-ferromagnetic metal. To improve the magnetoresistance effect, the channel can be a thin insulator, and the spin valve device is called a magnetic tunnel junction (MTJ). In a MTJ, the magnetoresistance results from the spin-polarized tunneling of conduction electrons between the two ferromagnetic layers. The tunneling current depends on the relative orientation of the magnetic moments of the two ferromagnetic layers.
The operation of the spin valve devices depends on the difference in the magnetization states of the two ferromagnetic layers. In practical devices, one of the ferromagnetic layers is pinned while the other ferromagnetic layer is free to change polarization. This free layer stores information based on the direction of the magnetic polarization with respect to the pinned layer. A variation of the spin valve structure is a pseudo spin valve wherein the pinned ferromagnetic layer is replaced by a thicker ferromagnetic layer with higher coercive strength. The higher coercive strength prevents the thicker ferromagnetic layer to change magnetic polarization during the change of magnetic polarization of the other ferromagnetic layer.
Further developments of the spin valve devices have led to a hybrid field of semiconductor and magnetic materials called spintronic (spin electronic). Semiconductors and magnetic materials have been studied extensively, but only recently devices having a combination of properties and functions of both materials were studied.
In a spintronic device, the non-ferromagnetic channel is a semiconductor material. However, spin injection from a ferromagnetic material to a semiconductor material is difficult due to the heterojunction between the ferromagnetic material and the semiconductor material. The heterojunction represents an important quantity which may place fundamental constraints on the expected efficiency of the injection process. Interfacial problems and the differences in carrier number and energy levels across the interface are possible difficulties in the heterojunction between the ferromagnetic material and the semiconductor material. At the interface, ferromagnetic metals have randomly oriented spins (called magnetically dead layer), and this creates a barrier to effective spin injection. In metals, the number of charge carriers is large and cannot be controlled easily. In semiconductors, the number of carriers (and therefore the resistivity) can be controlled easily by impurity doping. Conductivity mismatch problem of metal/semiconductor junction is severed in ferroelectric metal/semiconductor heterojunctions. Lattice mismatch could also lead to dislocations which act as spin scatterers and reduce spin injection efficiency.
A number of spintronic devices employing ferromagnetic metal/semiconductor heterojunction have been disclosed.
Johnson, U.S. Pat. No. 5,565,695, xe2x80x9cMagnetic spin transistor hybrid circuit elementxe2x80x9d, Oct. 15, 1996, discloses a hybrid memory cell consisting of a magnetic spin transistor and a semiconductor isolation transistor to improve isolation and signal to noise readout characteristics in a random access memory circuit.
Johnson, U.S. Pat. No. 5,652,445, xe2x80x9cHybrid Hall device and method of operationxe2x80x9d, Jul. 29, 1997, discloses a ferromagnetic gated field effect transistor having a ferromagnetic material in proximity to, or as part of, the gate over the conducting channel to provide improved devices that can be used easily and reliably in high density memory and logic environments.
Johnson, U.S. Pat. No. 5,654,566, xe2x80x9cMagnetic spin injected field effect transistor and method of operationxe2x80x9d, Aug. 5, 1997, discloses a hybrid field effect transistor using ferromagnetic materials for the source and drain with the spin-polarized conduction electrons injected from the ferromagnetic materials through a semiconductor channel.
Johnson, U.S. Pat. No. 6,297,987, xe2x80x9cMagnetoresistive spin-injection diodexe2x80x9d. Oct. 2, 2001, discloses a magnetoresistive spin-injection diode consisting a semiconducting channel, a single ferromagnetic layer and a barrier to prevent interdiffusion.
Kirczenow, U.S. Pat. No. 6,355,953, xe2x80x9cSpintronic devices and method for injecting spin polarized electrical currents into semiconductorsxe2x80x9d, Mar. 12, 2002, discloses atomically ordered interfaces between suitable semiconductor materials and suitable ferromagnetic materials to improve the injection of spin-polarized conduction electrons. Sato et al., U.S. Pat. No. 6,501,143, xe2x80x9cSpin-valve transistorxe2x80x9d, Dec. 31, 2002, discloses a spin valve transistor having a semiconductor emitter and a semiconductor collector, together with a spin valve device as a base to improve the magnetoresistance ratio and the ratio of the collector/emitter current.
Saito et al., U.S. Pat. No. 6,522,573, xe2x80x9cSolid-state magnetic memory using ferromagnetic tunnel junctionsxe2x80x9d, Feb. 18, 2003, discloses a solid-state memory using ferromagnetic tunneling element on a semiconductor substrate to achieve higher capacity, high reliability and high yield.
The spintronic devices in these prior art disclosures comprise a heterojunction of a ferromagnetic metal and a semiconductor material. This heterojunction between a metal and a semiconductor may present fundamental constraint on the efficiency of the spin injection process such as conductance mismatch, ferromagnetic dead layer, carrier number and energy mismatch at the heterojunction interface.
One proposed solution for the conductance mismatch at the ferromagnetic/semiconductor heterojunction is the insertion of a tunnel contact layer. This approach introduces additional complexity to the fabrication of the spin transistors.
Another solution to the conductance mismatch is a ferromagnetic semiconductor/semiconductor heterojunction since there is no interface problem with a magnetic semiconductor and semiconductor heterojunction. Oestreich in Nature, Vol. 402, Dec. 16, 1999, p. 735, xe2x80x9cInjecting spin into electronicsxe2x80x9d, reviews the progress of spin injection in electronic devices with two groups of Fiederling and Ohno showing feasibility of ferromagnetic semiconductor/semiconductor heterojunction at low temperatures. Fiederling et al. show that spin injection from a semimagnetic to a semiconductor is highly efficient, about 90%. The material used is unusual (BeMnZnSe II-VI semiconductor compound, Curie temperature is about a few degrees Kelvin), and acts as a spin aligner to inject to a GaAs semiconductor. Ohno et al. use GaMnAs (a group III-V semiconductor) as a spin aligner to inject holes through a GaAs spacer into a quantum well.
One of the difficulties of the ferromagnetic semiconductor/semiconductor heterojunction is the development of ferromagnetic semiconductor materials, especially at room temperature. EuS (Curie temperature Tc=16.6 K) is one of the very few natural ferromagnetic semiconductors. The majority of ferromagnetic semiconductors are diluted magnetic semiconductors fabricated in laboratory conditions.
Diluted magnetic semiconductors are semiconductors containing a large fraction of magnetic ions (Mn2+, Cr2+, Fe2+, Co2+). They are studied mainly on II-VI based materials because the 2+ magnetic ions are easily incorporated into the host II-VI crystal by replacing group II cations. But II-VI materials are difficult to dope to create p- and n-type, which makes the materials less attractive for semiconductor applications. Examples of II-VI based ferromagnetic semiconductors are (CdMn)Te, ZnSe, Zn1xe2x88x92xMnxO, GaN, Zn1xe2x88x92xCoxS (Tc=73 K to 300 K), CdCr2Se4 (Tc=113 K).
The obstacle of making diluted magnetic semiconductor from III-V group is the low solubility of magnetic element in the compounds. However, advances in thin film fabrication techniques such as MBE (molecular beam epitaxy) have made the formation of these non-equilibrium thin films possible. Examples of III-V based ferromagnetic semiconductors are Ga1xe2x88x92xMnxAs (Tc=110 K), (GaMn)Sb, (GaFe)Sb, Mn doped InAs (Tc=77 K).
A number of spintronic devices employing ferromagnetic semiconductor/semiconductor heterojunction have also been disclosed, though not for memory applications.
Kamiguchi et al., U.S. Pat. No. 5,962,905, xe2x80x9cMagnetoresistive elementxe2x80x9d, Oct. 5, 1999, discloses a magnetoresistive element in the form of a bipolar transistor with the base material being a ferromagnetic semiconductor to achieve large output and to show an amplifying effect.
Ohno et al., U.S. Pat. No. 6,482,729, xe2x80x9cMethod of generating spin-polarized conduction electron and semiconductor devicexe2x80x9d, Nov. 19, 2002, discloses a spin-polarized field effect transistor having a multilayer ferromagnetic semiconductor/semiconductor on top of the semiconductor source and drain of a regular field effect transistor to form the spin-polarized electronic injecting source and drain electrodes.
One of the difficulties with ferromagnetic semiconductor/semiconductor spin transistor is the low operating temperature of the ferromagnetic semiconductor, which make it unpractical in everyday applications.
Therefore it is advantageous to provide a ferromagnetic semiconductor/semiconductor heterojunction with an operating temperature higher than room temperature.
It is also advantageous to provide simplified spin-polarized field effect transistor for better control and fabrication.
It is also advantageous to provide simplified spin-polarized field effect transistor for memory applications.
Accordingly, a spintronic device with improved spin injection due to conductance matching is provided. The present invention spintronic device employs a plurality of ferromagnetic semiconductor/semiconductor heterojunctions to improve the spin injection from the ferromagnetic material into the semiconductor material.
The present invention also discloses the usage of room temperature ferromagnetic semiconductor materials such as iron doped titanium oxide for practical spintronic device applications.
The present invention also provides a spin transistor with the ferromagnetic semiconductor materials forming heterojunctions directly with the source and drain for simplified device fabrication process and potentially better spin injection.
The present invention also provides a magnetic random access memory application utilizing the disclosed spin transistor as a memory cell.
In one aspect of the invention, the spintronic device comprises two layers of ferromagnetic semiconductor materials (a source and a drain) sandwiching a layer of semiconductor material with the semiconductor layer forming two heterojunctions with the ferromagnetic semiconductor layers. A bias voltage or current is applied across the ferromagnetic layers, and the spin-polarized carriers (electrons or holes depending on the ferromagnetic semiconductor materials) are generated in the source ferromagnetic semiconductor layer, injected into the semiconductor layer through the ferromagnetic semiconductor/semiconductor heterojunction, and then collected at the drain ferromagnetic layer. Depending on the relative magnetic polarizations of the two ferromagnetic layers, most, some or only a few of the spin-polarized carriers can be collected, representing the various states of the spintronic device.
The ferromagnetic semiconductor can be a natural ferromagnetic semiconductor material such as EuS, or a diluted ferromagnetic semiconductor such as (CdMn)Te, Zn1xe2x88x92xMnxO, Zn1xe2x88x92xCoxS (Tc=73 K to 300 K), CdCr2Se4 (Tc=113 K). Ga1xe2x88x92xAs (Tc=110 K), (GaMn)Sb, (GaFe)Sb, Mn doped InAs (Tc=77 K).
In a preferred embodiment, for practical applications, the ferromagnetic semiconductor materials are room temperature ferromagnetic semiconductors, i.e. the Curie temperature of the ferromagnetic semiconductor materials is higher than 20xc2x0 C. (or 293 K). The ferromagnetic semiconductor material can be iron doped titanium oxide (FexTi1xe2x88x92xO2xe2x88x92)(see Wang et al., xe2x80x9cRoom temperature ferromagnetic semiconductor in Fe-doped reduced rutilexe2x80x9d, Phys. Rev. Lett., submitted), or cobalt doped titanium oxide.
The spintronic device can be fabricated on a substrate and can further comprise wiring layers electrically connected to the ferromagnetic semiconductor layers to provide carriers to the spintronic device from a bias voltage or current source. The spintronic device can further comprise a plurality of writing layer in the vicinity of the ferromagnetic semiconductor layers to supply a magnetic field to the ferromagnetic semiconductor layers to modify their magnetic polarization to change the magnetoresistance property of the spintronic device.
The semiconductor interface in the spintronic device can be highly doped to improve the contact between the ferromagnetic semiconductor layer and the semiconductor layer. The surface concentration of the highly doped region in the semiconductor layer can be higher than 1020 cmxe2x88x923 to ensure good contact between the ferromagnetic semiconductor layer and the semiconductor layer. The heterojunction of the ferromagnetic semiconductor layer and the semiconductor layer can be further improved by the salicidation of the semiconductor layer to improve the efficiency of injecting carriers from the ferromagnetic semiconductor layer to the semiconductor layer. The salicide can be titanium silicide, cobalt silicide, or nickel silicide. In the preferred embodiment of iron doped titanium oxide ferromagnetic semiconductor material, nearly perfect conductance match between the iron doped titanium oxide ferromagnetic semiconductor and the semiconductor material is possible with the Schottky barrier eliminated or reduced for greatly enhancing the spin injection efficiency.
The semiconductor in the spintronic device can be a II-VI, III-V or IV group semiconductor materials such as InSb, InAs, GaAs, InAsP, Si or Ge. In a preferred embodiment, the semiconductor material is chosen to have a good lattice match with the ferromagnetic semiconductor material to reduce dislocations and thus less spin scattering. The thickness of the semiconductor layer is preferably less than 150 nm for efficient spin injected electron transport through the source ferromagnetic material to the drain ferromagnetic material.
The majority carriers of the ferromagnetic semiconductor materials and the semiconductor material can be the same, meaning they are all of p-type semiconductors, or they are all of n-type semiconductor. The majority carriers of the ferromagnetic semiconductor materials and the semiconductor material can also be different to form various p-n junctions.
In other aspect of the invention, the spintronic device is a spin transistor. The spin transistor comprises a field effect transistor with a source ferromagnetic semiconductor layer and a drain ferromagnetic semiconductor layer forming heterojunctions of ferromagnetic semiconductor/semiconductor directly with the source and drain of the transistor. The field effect transistor in the spin transistor is a general-type field effect transistor comprising a semiconductor layer having a source and a drain separated by a channel, the conductance of which is controlled by a voltage applied to a gate located in the vicinity of the transistor channel and normally in physical contact with the transistor channel through a gate insulator. The general-type field effect transistor are described in detail in R. F. Pierret, xe2x80x9cChapter 1. The junction field effect transistorxe2x80x9d, p. 3-10, and xe2x80x9cChapter 5. MOS field effect transistorsxe2x80x9d, p. 81-85 in Modular series on solid state devices, R. F. Pierret, G. W. Neudeck, Editors, 1983, Addison-Wesley Publishing Company, hereby incorporated by reference.
The conductance of the channel can also be controlled by the relative magnetic polarization of the ferromagnetic layers. If the magnetization in those ferromagnetic layers are parallel, the conductance is higher than if they are antiparallel or partially antiparallel. In this aspect, the spin transistor is a memory cell with the data stored is the relative magnetization states of the source and drain ferromagnetic layers. The magnetization states of the ferromagnetic layers can be modified by a magnetic field generated by external write currents through a plurality of conductive write plates located in the vicinity of the ferromagnetic layers. A first write plate can be located in the vicinity of the drain ferromagnetic semiconductor layer and a second write plate can be located in the vicinity of the source ferromagnetic semiconductor layer.
The spin transistor can be fabricated on a substrate and can further comprise wiring layers electrically connected to the ferromagnetic semiconductor layers to provide carriers to the spintronic device. The spin transistor can further comprise wiring layer electrically connected to the gate to control the conductance of the transistor channel. The spintronic device can further comprise a plurality of wiring layers electrically connected to the write plates to supply the write current to modify the magnetization of the ferromagnetic layers.
The spin transistor is preferably having a short channel length of less than 150 nm for efficient spin injection from the source through the surface channel to the drain region. The source and drain regions in the spin transistor are preferably highly doped to provide conduction carriers. The thickness of the highly doped source and drain regions is preferably less than 100 nm to enhance the magnetoresistance effect. The surface concentration of the highly doped source and drain regions in the field effect transistor can be higher than 1020 cmxe2x88x923 to ensure good contact between the ferromagnetic semiconductor layer and the semiconductor layer. The heterojunction of the ferromagnetic semiconductor layer and the semiconductor layer can be further improved by the salicidation of the source and drain regions to improve the efficiency of injecting carriers from the ferromagnetic semiconductor source layer to the semiconductor layer. The salicide can be titanium silicide, cobalt silicide, or nickel silicide. In the case of iron doped titanium oxide ferromagnetic semiconductor material, nearly perfect conductance match between the iron doped titanium oxide ferromagnetic semiconductor and the semiconductor material is possible. Schottky barrier can be eliminated or reduced to greatly enhance the spin injection efficiency. Since the highly doped junction depth is very shallow, the resistivity of the highly doped junction is much higher than that of the ferromagnetic layer. When the channel is turned on and a bias voltage is applied to the drain electrode, spin electrons or holes from the source ferromagnetic layer is injected through the surface channel and is collected by the drain junction, then flow through the ferromagnetic drain electrode to the collector electrode. Thus beside the normal spin transistor action, a series resistor is added to the drain of the transistor. Since the resistivity of this series resistor is spin dependent, it enhances the memory device output signal.
The spin transistor can further comprise a p-well or n-well region for isolation. The transistor channel can be p channel or n channel. The source and drain regions can be highly doped p+ or n+.
The ferromagnetic semiconductor can be a natural ferromagnetic semiconductor material such as EuS, or the ferromagnetic semiconductor can be a diluted ferromagnetic semiconductor such as (CdMn)Te, Zn1xe2x88x92xMnxO, Zn1xe2x88x92xCoxS (Tc=73 K to 300 K), CdCr2Se4 (Tc=113 K), Ga1xe2x88x92xMnxAs (Tc=110 K), (GaMn)Sb, (GaFe)Sb, Mn doped InAs (Tc=77 K).
For practical applications, the ferromagnetic semiconductor materials are room temperature ferromagnetic semiconductors, i.e. the Curie temperature of the ferromagnetic semiconductor materials is higher than 25xc2x0 C. (or 298 K). The ferromagnetic semiconductor material can be iron doped titanium oxide (FexTi1xe2x88x92xO2xe2x88x92), or cobalt doped titanium oxide.
The semiconductor in the spintronic device can be a II-VI, III-V or IV group semiconductor materials such as InSb, InAs, GaAs, InAsP, Si or Ge. The semiconductor material is chosen to have a good lattice match with the ferromagnetic semiconductor material to reduce dislocations and thus less spin scattering.
The majority carriers of the ferromagnetic semiconductor materials and the semiconductor material can be the same, meaning they are all of p-type semiconductors, or they are all of n-type semiconductor.
In other aspect of the invention, the spintronic transistor is a memory cell to store a data state. The memory cell consists of only a spin transistor but functions as an one-resistor-one-transistor (1R1T) memory cell with the resistor is the resistance of the spintronic transistor channel. The magnetic memory cells can be arranged in a traditional x-y array for high density memory fabrication. A magnetic random access memory includes an array of memory cells, together with other circuit components such as a row decoder, a column decoder, a write circuit to write to the memory cell array, control circuitry to select the correct memory cell resistor, and a sense amplifier to amplify the signal before sending it to the voltage comparator.